There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM cells.
One example of a flash memory system uses the NAND structure, which includes arranging multiple charge-storage transistors acting as memory cells in series, sandwiched between two select gates. A NAND array has a number of memory cells, such as 8, 16, or even 32, connected in as a string of memory cells (NAND string) between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings.
To program a flash memory cell, a program voltage is applied to the control gates and the bit line is grounded causing the threshold voltage of the cell to be raised. Because the program voltage is applied to all cells connected to a word line an unselected cell (a cell that is not to be programmed) on the word line may become inadvertently programmed. The unintentional programming of the unselected cell on the selected word line is referred to as “program disturb.”
Continuous efforts are being made to improve programming techniques of NAND memory cells so that more information can be stored efficiently and program disturbs are prevented.
Therefore there is a general need for high performance and high capacity non-volatile memory. In particular, there is a need for a compact non-volatile memory with enhanced read and program performance having an improved processor that is compact and efficient, yet highly versatile for processing data among the read/writing circuits.